Field of the Invention
The invention relates to the field of semiconductor device manufacturing, more particularly, to a semiconductor cooling method and a method of heat dissipation.
Description of the Related Art
With the ever-increasing integration, the number of memory cells on a single chip increased dramatically, the increase of chip area, the growth of the connection between the cells both affects circuit speed and takes a lot of work area, seriously affecting the integrated circuit further enhance integration and operating speed. Thus new technology idea of three-dimensional integration generated. In the manufacture of advanced three-dimensional integrated circuits, typically requires mixed bonding process for two wafers containing metal and dielectric thin films, two wafers can make into one by mixed bonding process. The advantages of three-dimensional integration are: firstly, improve the packaging density. Multilayer device overlapping structure can exponentially increase chip integration. Secondly, increase the operating speed of the circuit. Overlapping structure shortens cell attachment, and makes parallel signal processing become possible, in order to achieve high speed operation of the circuit. Moreover, achieve new multifunctional devices and circuitry. For example, put the functional devices like photovoltaic devices and integrated circuits together to form a new functional system.
In the case of VLSI development increasingly approaching the physical limits, the three-dimensional integrated circuit having advantages in both physical size and costs is an effective way to prolong Moore's Law and solve the problem of advanced packaging. Wafer bonding technology is one of the key technologies of three-dimensional integrated circuit, especially mixed bonding technology enables interconnection of thousands of chips at the same time of two pieces of wafer bonding, which can greatly improve chip performance and save costs. Wafer bonding is a technology bonding two wafers or more than two pieces of wafers having different devices together, to make ions on wafer surface interact to produce covalent bond, and allow two wafers band together by atomic bonds rather than using bonding medium, this feature can meet the production requirements of microelectronic materials, optoelectronic materials and nanoscale MEMS components etc, and combine with different lattice, different types of single crystalline or polycrystalline material, and produce luminescent devices and photoelectric devices having special physical or chemical properties by different physical properties (such as thermal conductivity, mechanical strength), chemical properties (e.g. active energy) and electronic properties (e.g., electronic energy levels), etc. of the combined materials, or mobile communication devices for the development of low-voltage low-power, or low energy, high temperature resistant electronic devices and optoelectronic devices with emphasis on the use for space vehicle.
Meanwhile however, three-dimensional bond will generate a lot of heat, which will stack in the interior of the chip after bonding, so that make the stability of the device decline, thereby affecting the performance of the device. With the proposition of three-dimensional integration makes the device structure become more compact, then is faced with a problem: Since the three-dimensional integrated circuits is mostly multi-layer stack structure, the overall thermal power is increasing, but the surface area to volume ratio is falling, so the traditional flat cooling technology is no longer able to meet the cooling requirements of three-dimensional integrated circuit, and if long-term work under high temperature conditions may cause the device burned, so considering the heat dissipation is also a very essential question in bonded wafers.
China Patent (CN103107128A) discloses a metallic bonding method and bonding structure of three-dimensional chip architecture. Comprising chemical mechanical planarization process to top chip copper; depositing a silicon nitride layer on the surface after chemical mechanical planarization; etching the silicon nitride layer attached on top chip copper to form a groove, the bottom of the groove is the top chip copper; chemical mechanical planarization process to bottom chip copper; etching bottom silicon dioxide layer to make copper highlight; surface activation treatment after the etch of the bottom silicon dioxide layer; aligning and bonding copper of top chip and bottom chip; annealing the chip after bonding. However, this patent application does not cover how to solve the heat accumulation problem in existing bonding process.
China Patent (CN 102593087A) discloses a mixed bonding structure for three-dimensional integration, includes a first substrate; the first substrate has bonded interconnect metal electrically connected to the first substrate, the bonded interconnect metal forms invagination corresponding to the other end connected to the first substrate; the first substrate is covered with first dielectric adhesive layer around the bonded interconnect metal, the first dielectric adhesive layer surrounds the bonded interconnect metal and the height of the first dielectric adhesive layer is less than the edge height of the bonded interconnect metal. However, this patent application does not cover how to solve the heat accumulation problem in existing bonding process.
China Patent (Publication No.: CN 202394961U) discloses a semiconductor wafer having a cooling column, wherein: said semiconductor wafer comprises: a plurality of chips; an insulating connecting region which connects and supports said plurality of chips, wherein said plurality of chips equidistantly arrange with the form of an array in the insulating connection region; a re-wiring layer, formed on a first surface of the plurality of chips and the insulated connection region; a metal layer, formed on a second surface of the plurality of chips and the insulated connection region; and a plurality of cooling columns, formed on the metal layer corresponding to the position of each chip. This patent improves the effect of heat dissipation by setting the cooling columns, which however does not apply for wafer bonding process, since two wafers fitting together after bonding, heat-sinking capability of the two contact surfaces is limited. The patent may bring high difficulties in processing and high production costs and other misgivings in the application and actual production preparation, it has some limitations.